This invention relates to the provision of conductive paths between devices and a metallization layer or between metallization layers of integrated circuits, and to a process for forming such conductive paths or electrically conductive plugs by the selective deposition of tungsten.
In an integrated circuit, the devices and elements formed in the substrate are interconnected with metallic (e.g. aluminum) leads which are typically formed by sequential deposition, masking and etching, generally referred to as metallization. Such metallization usually provides for a layer of metallization on top of a layer of insulating oxide or glass and the insulating oxide on which the metal is deposited generally includes openings or windows for the formation of metallized contacts to silicon or polysilicon, or metallized vias to another layer of metallization.
Tungsten is employed for various purposes in manufacturing semiconductor integrated circuits. For example, in making such integrated circuits and other solid state devices, the tungsten serves to wire the electrical contacts required between an overlying conductive layer and an underlying region separated therefrom by a layer of dielectric material. The overlying layer is typically a metal and the underlying region is typically a doped semiconductor region, salicide, or another metal layer. The contact between the overlying and underlying materials is through the conductive filled openings or windows commonly referred to as "vias" (when the wiring is of metal to metal) or "contacts" (when the wiring is to source-drain, salicide, or polysilicon).
It is known to provide for conductive filled contact and via openings to allow for openings of reduced size and to allow for greater device densities.
One approach to filling such openings is described in Saia et al, "Plasma Etching Methods for the Formation of Planarized Tungsten Plugs Used in Multilevel VLSI Metallizations", J. Electrochem. Soc.: SOLID-STATE SCIENCE AND TECHNOLOGY, Vol. 135, No. 4, pp. 936-940 (April, 1988) and is illustrated and described hereinafter in the description of FIGS. 1A to 1D.
Another approach to filling such openings is described in Farb, PCT International Publication Number WO 88/04831 published June 30, 1988 and is illustrated and described hereinafter with reference to FIGS. 2A-2G.
Yet another approach to filling such openings is disclosed in Shoji Madokoro, Japanese patent publication Kokai No. 63-764563, Apr. 6, 1988, (Application Ser. No. 61-219644 filed Sept. 19, 1986) entitled "Manufacture of Multilayer Interconnection" and is illustrated and described hereinafter with reference to FIGS. 3A-3D.
Various problems exist with such prior art techniques particularly when filling multiple apertures of varying depths primarily because the various depths are filled to overflowing and have to be etched back to provide a planar surface. All of such techniques generally require additional expensive and time-consuming steps of deposition; masking and etching steps to remove "nail heads" or overflow of material; or such techniques must align critical contacts more than once, or rely on uniform sidewall nucleation in a selective mode, etc.